1. Field of the Invention
The present invention relates to a semiconductor device whereby memory can operate as a logic circuit.
2. Description of the Related Art
Heretofore, semiconductor devices, such as LSIs (Large Scale Integration) and so forth, have been manufactured through many processes, such as functional design, logic circuit design, wafer manufacturing, assembly, and so forth. The manufacturing process thereof has been suitable for mass production for the same product, but has been unsuitable for small-lot production of various products, since such production is costly.
Therefore, manufacturing technology of devices such as such as FPGAs (Field Programmable Gate Array) and so forth, has been developed such that even if the same semiconductor devices is manufactured in mass, the customer side can handle these as separate products. An FPGA is a semiconductor device, such as an LSI or the like, whereby a logic circuit can be programmed after manufacturing.
However, an FPGA is configured of various types of components, such as a logic circuit, wiring, switch, and so forth, so there has been a problem in that a multilayer wiring configuration of the number of wiring layers on a semiconductor process, and advanced manufacturing technology, are needed.
As a solution, a technique for operating memory as a logic circuit has been developed. For example, with Japanese Unexamined Patent Application Publication No. 2003-149300, a technique has been disclosed regarding a semiconductor device wherein a plurality of memory are connected by wiring, and predetermined truth values are written in the memory so as to output predetermined data as to predetermined address input, thereby operating as a logic circuit.
Also, with Japanese Unexamined Patent Application Publication No. 2003-224468, a technique has been disclosed regarding a semiconductor device wherein truth table data is written in memory, such as SRAM (Static Random Access Memory) or the like, and an address is taken as input, and data is taken as output, thereby operating as a logic circuit.
Note however, with the semiconductor device according to Japanese Unexamined Patent Application Publication No. 2003-149300, there has been a problem wherein in a case in which the truth-values in the memory are rewritten, reconnection of wiring is needed.
Also, with the semiconductor device according to Japanese Unexamined Patent Application Publication No. 2003-224468, there has been a problem wherein memory cell blocks in which multiple memory cells for storing a predetermined amount of data are collected are disposed in an arrayed manner, and the data from a single memory cell block is output to only the two of adjacent four memory cell blocks (e.g., right and bottom of the left, right, top and bottom), so it is difficult to operate as a logic circuit for feeding back data (returning to the original memory cell block). Also, the appropriate scale of memory cell block (the number of inputs and the number of outputs) has not been taken into consideration.